1. Field of the Invention
The present invention relates to CMOS integrated circuits, and in particular to a CMOS NOR gate circuit.
2. Description of the Related Art
Digital logic circuits, including CMOS NOR gate circuits, are well known in the art. Referring to FIG. 1, a CMOS NOR gate 100 typically uses P-channel MOS transistors 104 and 105 as pull-up devices and N-channel MOS transistors 106 and 107 as pull-down devices. For example, if the input signals on lines 101 and 102 are low, the output signal on line 103 is high because of the low impedance connection to voltage source Vcc through turned-on P-channel transistors 104 and 105, and the high impedance connection to ground through turned-off N-channel transistors 106 and 107. In contrast, if the input signal on lines 101 and 102 is high, the path to voltage source Vcc is blocked and NOR gate 100 provides a low impedance connection to ground, thereby providing a low signal on line 103.
The output line 103 of NOR gate 100 is typically connected to a CMOS buffer (not shown) which functions as a driver for NOR gate 100. Note that an inverter (also not shown) coupled to line 103 transforms NOR gate 100 into an OR gate. Thus, a NOR gate circuit is used to implement both OR or NOR logic functions.
In digital logic circuits, both high speed and low power consumption are desired. Although NOR gate 100 provides low power consumption, its speed of switching voltages on line 103 is relatively slow. NOR gate 200, shown in FIG. 2, increases the speed of switching on line 203 by providing a strong pull-up transistor 204 for low to high voltage transistor and providing two strong pull-down transistors 206 and 207 for high to low voltage transitions. However, if pull-up transistor 204 is too strong, then NOR gate 200 consumes a significant amount of power when either transistors 206 and 207 are conducting, thereby creating an unstable, intermediate voltage level on line 203. Consequently, any driver coupled to line 203 also burns power. Furthermore, if input signals on lines 201 and 202 are at an intermediate level, NOR gate 200 operates at low efficiency because transistors 206 and 207 are turned on or off weakly, thereby also providing an unstable signal on line 203.